Flexible Multi-ASIP SoC for Turbo/LDPC Decoder

International audienceIn order to meet flexibility and performance constraints of current and future digital communication applications, multiple ASIPs combined with dedicated communication and memory architectures are required. In this work we consider the design of an innovative universal channel decoder architecture model by unifying flexibility-oriented and optimization-oriented approaches. Towards this objective, we have designed a flexible and scalable multiprocessor platform based on a novel ASIP architecture for high throughput turbo/LDPC decoding. The proposed platform supports turbo and LDPC codes of most emerging wireless communication standards (WiFi, WiMax, LTE, and DVB-RCS). Energy-aware optimisation techniques have been also proposed and implemented. Finally, a fully functional FPGA demonstrator is available and the proposed Multi-ASIP architecture has been successfully integrated into a new generation telecom chip

Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET

For the rapid adoption of new and aggressive technologies such as ambipolar Silicon NanoWire (SiNW), addressing fault-tolerance is necessary. Traditionally, transient fault detection implies large hardware overhead or performance decrease compared to permanent fault detection. In this paper, we focus on on-line testing and its application to ambipolar SiNW. We demonstrate on self - checking ripple - carry adder how ambipolar design style can help reduce the hardware overhead. When compared with equivalent CMOS process, ambipolar SiNW design shows a reduction in area of at least 56% (28%) with a decreased delay of 62% (6%) for Static (Transmission Gate) design style

Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications

Several nanowire technologies have emerged recently, providing a way to continue the scaling down of complementary metal-oxide-semiconductor (CMOS) technology. The opportunities offered at the level of logic circuit design depend on the technology properties, and some applications seem to be suitable for specific technologies. In this paper, we survey three nanowire technologies that yield nanowire arrays. All of them depend on the photolithography limit but they differ with respect to the processing and the device properties. We show the ability of the spacer technique to yield nanowires with a pitch below the photolithography limit. We introduce the nanowire crossbars in a pure CMOS process and extract the parasitics that affect nanowire crossbar circuits. Vertically stacked nanowires are also demonstrated with the deep reactive ion etching (DRIE) process. We link the surveyed processes to specific circuit architectures that are optimized for the considered technologies. A nanowire decoder for sub-lithographic nanowires is demonstrated with the smallest size compared to other competing technologies. Then an optimized crossbar multiplexer is presented, which takes into account the presence of parasitics. Finally, a general library of logic gates based on vertically stacked nanowires is evaluated showing a smaller area and a better performance than CMOS

3D advanced integration technology for heterogeneous systems

International audience3D integration technology is nowadays mature enough, offering today further system integration using heterogeneous technologies, with already many different industrial successes (Imagers, 2.5D Interposers, 3D Memory Cube, etc.). CEA-LETI has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this paper, a short overview of some recent advanced 3D technology results is presented, including some latest 3D circuit's description

Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs

Emerging Non-Volatile Memories (eNVMs) such as Phase-Change RAMs (PCRAMs) or Oxide-based Resistive RAMs (OxRRAMs) are promising candidates to replace Flash and Static Random Access Memories in many applications. This paper introduces a novel set of building blocks for Field-Programmable Gate Arrays (FPGAs) using eNVMs. We propose an eNVM-based configuration point, a look-up table structure with reduced programming complexity and a high-performance switchbox arrangement. We show that these blocks yield an improvement in area and write time of up to 3x and 33x respectively vs. a regular Flash implementation. By integrating the designed blocks in a FPGA, we demonstrate an area and delay reduction of up to 28% and 34% respectively on a set of benchmark circuits. These reductions are due to the eNVM 3-D integration and to their low on-resistance state value. Finally, we survey many flavors of the technologies and we show that the best results in terms of area and delay are obtained with Pt/TiO2/Pt stack, while the lowest leakage power is achieved by InGeTe stack

Disruptive Logic Architectures and TechnologiesFrom Device to System Level /

XIV, 190 p.online resource

Procédé d'optimisation du fonctionnement d'un circuit intégré multiprocesseurs, et circuit intégré correspondant

L'INVENTION CONCERNE UN PROCEDE D'OPTIMISATION DE FONCTIONNEMENT QUI S'APPLIQUE A UNE PUCE DE CIRCUIT INTEGRE MULTI-PROCESSEUR. CHAQUE PROCESSEUR TRAVAILLE AVEC UN PARAMETRE VARIABLE, PAR EXEMPLE SA FREQUENCE D'HORLOGE, ET L'OPTIMISATION COMPREND LA DETERMINATION EN TEMPS REEL D'AU MOINS UNE DONNEE CARACTERISTIQUE ASSOCIEE AU PROCESSEUR (TEMPERATURE, CONSOMMATION, LATENCE), LE TRANSFERT DES DONNEES CARACTERISTIQUES VERS LES AUTRES PROCESSEURS, LE CALCUL PAR CHAQUE PROCESSEUR DE DIFFERENTES VALEURS D'UNE FONCTION D'OPTIMISATION DEPENDANT DE LA DONNEE CARACTERISTIQUE DU BLOC, DES DONNEES CARACTERISTIQUES DES AUTRES BLOCS, ET DU PARAMETRE VARIABLE, LA FONCTION ETANT CALCULEE POUR LA VALEUR ACTUELLE DE CE PARAMETRE ET POUR D'AUTRES VALEURS POSSIBLES, PUIS LA SELECTION, PARMI LES DIFFERENTES VALEURS DE PARAMETRE, DE CELLE QUI DONNE LA MEILLEURE VALEUR DE LA FONCTION D'OPTIMISATION, ET ENFIN L'APPLICATION DE CETTE FREQUENCE AU PROCESSEUR POUR LA SUITE DE L'EXECUTION DE LA TACHE

Architecture de mémoire haute densité à base d'électronique moléculaire tolérante à un très grand nombre de défauts

L'électronique moléculaire, partie intégrante des nanotechnologies, résulte de la convergence de différents domaines : la microélectronique, la physique, la chimie ou encore la biologie. L'engouement suscité s'explique par l'espoir de trouver un complément faible coût, voire une alternative viable à l'électronique CMOS sur silicium actuelle, dont les perspectives d'évolution restent floues au-delà de 2015/2020 et dont le coût de fabrication actuel augmente de façon exponentielle. Les dispositifs à base d'électronique moléculaire apparaissent comme des candidats potentiels à l'intégration dans les mémoires du futur. En effet, leur utilisation permettrait d'obtenir, de part leurs dimensions nanométriques, des densités très élevées, bien au-delà de la roadmap silicium, tout en réduisant les coûts de fabrication grâce aux procédés d'auto-assemblage et d'intégration tridimensionnelle. Cependant, l'état de l'art actuel indique qu'il n'existe pas de modélisation appropriée à des simulations complexes et qu'à cette échelle, les variations technologiques d'un composant à l'autre seront très élevées. Les travaux de recherche présentés dans ce manuscrit de thèse proposent un nouveau type d'architecture de mémoire de très haute densité et tolérante aux dispersions, à base de transistor moléculaire à nanofils à effet de champs (NW-FET moléculaire). L'étude présente un modèle continu VHDL-AMS du transistor moléculaire, et deux niveaux de modélisation VHDL-AMS d'une nouvelle cellule mémoire moléculaire haute densité. Enfin, différentes techniques de tolérance aux fortes dispersions (jusqu'à 25% de variations des caractéristiques des dispositifs de base) sont évaluées.Much of the nanotechnology research taking place today is confined in the area of material science, electrical engineering, quantum and device physics, chemistry and even biology. This is actually a problem as there is little research undertaken at the circuit and architectures levels to integrate these new nano-devices. We are confronted to the difficulty of the bottom-up approach. The main limitation is the absence of fast and functional electrical models that would permit to explore, in a *reasonable* time, new approaches for signal processing based on nanotechnology's specific functionalities. Paradoxically, because there is no real development on computing paradigms adapted to nanotechnology, research ongoing on new molecular electronics devices have little choice but to follow a classical approach, that is to say, the quest for the ultimate transistor. However, the need for new architectures is real as it is known that much of the new devices being studied and developed will hardly be compatible with today's design flow, circuits and architectures. Some of them *might* be one day fully integrated in today's circuit fabrication, but even in this case, reliability, defect tolerance and fault tolerance will be the main issue for manufacturers. By proposing an intermediate method between the standard CMOS design-flow and the revolutionary molecular-electronics *bottom-up* approach, the aim of this methodology is to transfer the complexity and the cost needed to control a state of the art technology, toward the development of new architectures and algorithms compensating intrinsic technological dispersions, hopefully at a lower cost.PARIS-Télécom ParisTech (751132302) / SudocSudocFranceF